If you’ve been reading about the electronics industry recently, you’ve probably heard about Intel announcing that it was going to begin making all new transistors in 3 dimensions back in May. It was recently discussed by IEEE Spectrum, and a very good history of the transistor is covered. Even Kurzweil is claiming that his prediction for “3D Chips” has come true: While not yet commonly used in all chips, most semiconductors fabricated today for MEMS and CMOS image sensors are in fact 3D chips using vertical stacking technology.

However, there are fine technical definitions of “3d” and there are commonly accepted definitions of “3d.” And this is a case where the definition of “3d” is probably not the one you are thinking of.

Some of you might be old enough to remember DOOM in its original release. It was a ground breaking innovation for its time because it introduced REAL 3D! in a video game for the first time. Except that it actually didn’t. That might come as a shock to all of you who’ve fallen off a ledge into a pool of toxic goo, but the reality is that DOOM made some very clever use of what was still essentially a 2D world. Nothing actually could exist “above” anything else. If you “climbed” a set of stairs, the space at the top of the stairs couldn’t be “above” the space at the bottom of the stairs. You could raise any given square of space to any height, but that square was still the only thing that could occupy that 2D grid co-ordinate.

In much the same way, Intel’s move to FIN-FET design is adding an element of 3D to transistor design. It creates a raised “Fin” of the channel material enabling the gate to wrap around 3 sides, increasing the effectiveness of the gate enormously. But, much like DOOM, it’s not 3d in the manner which allows a chip to be designed with layers of circuits placed on top of other layers.

That is not to say that there are not major advantages to this move, because by increasing the efficiency of the gate has tremendous effects on the power consumption of a transistor, which in turn will lead to lower heat production, less “leakage” across the transistor in it’s off state, and the ability to more densely pack transistors, enabling continuing progress in silicon for at least three more “generations.” But as Brian Wang points out, it has a probable limit of 0.7nm size, before the leakage and parasitic capacitances render it problematic to reduce size further.

But again, that’s several years away yet. From a practical standpoint, the “value” of this move to the end user will prove significant. This greater efficiency per transistor magnified over the billions in a processor means a major improvement in energy consumption. Combined with other energy saving advances, such processors will likely radically extend the time between recharges needed for many portable devices, as well as lower the operating costs of standard computers. The less a processor consumes, the lower the heat it generates, the less cooling is needed, the lower the overall energy cost become. While that might not seem like much to a home user, it’s a huge concern to businesses of every size that rely on numerous computers to run their business.

It’s not the “3D” chip architecture you might have thought it was. It is however a significant step towards it.